This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
This course describes the system design flow and interfaces that can be used for data movement in the Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster developme...
With the Versal Adaptive Compute Acceleration Platform (ACAP) family XILINX introduces versions of these FPGA with a special feature, the AI Engine. The AI Engine offers high performance, low latency capabilities for ...
This power workshop combines the contents of the PLC2 workshops “Compact Versal ACAP for Hardware Designers” and “Compact Versal ACAP for Software Designers”. In the course, the necessary and in-depth knowledge is imp...
With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...
This is Session 2 in the Versal Adopter Series - which will cover the most essential aspects of programming.Topics Include:AIE data movement and interfacesScalar and vector data-typesMemory managementInstrinsic and C+...
This is Session 4 in the Versal Adopter Series -Topics Include:Programming the A72, R5F and Platform Management ControllerRunning AIE graph code and RTP (run-time-parameters) on PSOverview of PS instruction set-archit...
This is Session 6 in the Versal Adopter Series -Topics Include:Utilizing and optimizing programmable logicCLB structureMemory resources, LUT-RAM, BRAM, URAMUsing and optimizing DSP58 slicesPros and cons of HDL coding ...
This is Session 3 in the Versal Adopter Series - which covers creating efficient chip-level communication schemes.Topics Include:NoC resources and programmingStructure, data-packeting, managing CDCsQoS assignments and...
