With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity, Memory Management, DSP Engines and AI Engines, which in particular enable software and DSP applications to be parallelized and partitioned in hardware to enable the optimal hardware units usage for the specific task. In this workshop you will be familiarized with the architecture in order to be able to use the building blocks optimally for demanding tasks. Versal offers multi processor and SMP support, AI engines, DSP engines also supporting floating point and programmable logic (PL) as well. The technical features and optimal use of the components are described in order to compile software and hardware functions on specific hardware units. There exist many ways of optimization in order achieve better results in performance, power reduction, latency reduction and higher reliability in functional safety. In particular, function partitioning will bean important aspect here, which requires good knowledge of this architecture. Network-on-Chip (NoC) provides a hardware bus interfacing which can be configured to get the appropriate throughput and priority management for multi-parallel data transfers on-chip. The workshop is particularly suitable for system engineers and developers in the planning phase of complex tasks, such as acceleration based development in cloud based datacenters or for the edge product.
8/21/2025 - 8/22/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Stuttgart - TBD PLC2 Venue Address : TBD,Stuttgart,GERMANY
11/17/2025 - 11/18/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Munchen - TBD PLC2 Venue Address : TBD,Munchen,GERMANY
