Designing with the Versal Adaptive SoC: Design Methodology
Course Details
Length:
28 Hours
Number of Labs:
9
Number of Chapter:
22
Current Version:
2024.2
Number of Demos:
0
Overview
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and thermal solutions to enhance the performance of a design.
The emphasis of this course is on:
Demonstrating the embedded software development flow for Versal devices
Demonstrating the AI Engine development flow
Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
Leveraging the Power Design Manager (PDM) tool for power estimation
Identifying Versal adaptive SoC power and thermal solutions
Enabling top-level RTL flows for Versal devices
Applying common timing closure techniques
Performing device configuration and debugging
Improving Versal adaptive SoC system performance
Performing system-level simulation
What's New:
Revamped the course to be a three-day course with the addition of new content and features
Added new modules:
AI Engine Programming: Kernels and Graphs
AI Engine System Partitioning
Enabling Top-level RTL Flows
Optimizing SLR Crossings in SSI Technology
Segmented Configuration
Added new labs on:
Embedded software development
AI Engine system partitioning
Kernels and graphs
Introduced the PDI debug utility in the Configuration and Debugging module
All labs have been updated to the latest software versions
