Classroom - Designing with Versal AI Engine 1 - Architecture and Design Flow

This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), and how to analyze a kernel program by using various debugger features.

The emphasis of this course is on:
  • Describing the AI Engine (AIE) architecture
  • Illustrating the Versal AI Engine tool flow  
  • Designing with single AI Engine kernels and analyzing the performance of scalar and vectorized kernels using the Vitis™ unified software platform  
  • Designing with multiple AI Engine kernels using data flow graphs with the Vitis Unified IDE  
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)  
  • Analyzing and debugging kernel performance  
  • Describing the AIE-ML architecture  
  • Illustrating the programming model for the AIE-ML

9/2/2025 - 12/3/2026
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
10/27/2025 - 10/28/2025
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
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Venue : NLD - Heesch - CoreVision Headquarters
Address : Cereslaan 24,Heesch,NETHERLANDS
10/27/2025 - 10/28/2025
Time Zone : (GMT+09:00) Seoul
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Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA
2/9/2026 - 2/11/2026
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Venue : ESP, Madrid - Universidad Autonoma de Madrid
Address : Fco Tomas y Valiente 11,School of Engineering,Madrid,SPAIN