Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered.
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
This course covers the advanced features of the AMD Versal™ adaptive SoC AI Engine, including kernel function development, optimizing an AI Engine kernel program, using AI Engine APIs and filter intrinsics, and debugg...
With the Versal Adaptive Compute Acceleration Platform (ACAP) family XILINX introduces versions of these FPGA with a special feature, the AI Engine. The AI Engine offers high performance, low latency capabilities for ...
This power workshop combines the contents of the PLC2 workshops “Compact Versal ACAP for Hardware Designers” and “Compact Versal ACAP for Software Designers”. In the course, the necessary and in-depth knowledge is imp...
With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, integrated networking solutions, and the programmable net...
