This course covers the AMD Versal™ AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AMD...
This course describes the system design flow and interfaces that can be used for data movement in the AMD Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster devel...
This course covers the advanced features of the AMD Versal™ adaptive SoC AI Engine, including kernel function development, optimizing an AI Engine kernel program, using AI Engine APIs and filter intrinsics, and debugg...
This course covers the AMD Versal™ AI Engine architecture and memory modules, programming the AI Engine (kernels and graphs), using the DSP Library, developing AI Engine designs using AMD Vitis™ Model Composer, and de...
This course:Versal AI Engine Data MovementSystem Design FlowIntroduction to AI Engine APIs for Arithmetic OperationsAdvanced Graph Input Specifications
This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the ...
This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AM...
Join us for this FREE WORKSHOP focused on the Versal AI Core series VC1902 adaptive SoC—a powerful solution for DSP applications. We’ll explore how to effectively use the AMD Model Composer tool and the VCK190 evaluat...
Are you ready to dive into the heart of the AMD Versal Adaptive SoCs? This FREE WORKSHOP delves into the details of the AI Engines (AIE) at the core of unparalleled performance, vector processing, and throughput. Topi...
In this seminar we would explore the AMD Versal™ adaptive SoC heterogeneous architecture and concentrate in three important aspects of the architecture (i) the programmable network on chip (NoC), (ii) the memory inter...
