Designing with Versal AI Engine: Architecture and Design Flow - 1
Course Details
Length:
22 Hours
Number of Labs:
6
Number of Chapter:
18
Current Version:
2025.1
Number of Demos:
0
Overview
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), and how to analyze a kernel program by using various debugger features.
The emphasis of this course is on:
Describing the AI Engine (AIE) architecture
Illustrating the Versal AI Engine tool flow
Designing with single AI Engine kernels and analyzing the performance of scalar and vectorized kernels using the Vitis™ unified software platform
Designing with multiple AI Engine kernels using data flow graphs with the Vitis Unified IDE
Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic
Analyzing and debugging kernel performance
Describing the AIE-ML architecture
Illustrating the programming model for the AIE-ML
Describing the AIE-ML v2 architecture for Versal AI Edge Series Gen 2 devices
What's New:
Overview of the AMD Versal Adaptive SoC Architecture module: Added information on Versal AI Edge Series Gen 2 and Prime Series Gen 2 architectures
Introduction to the AIE-ML v2 Architecture module: New
All the labs have been updated to the latest software versions
