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Classroom - Designing with the Versal Adaptive SoC: Architecture and Methodology
This course helps you to learn about Versal™ ACAP architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal ACAPDescribing the different engines available in the Ve...

Classroom - Designing with the Versal Adaptive SoC: Design Methodology
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and ther...

Classroom - Designing with the Versal Adaptive SoC: Hardware Debug
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers Chip ScoPy...

Classroom - Designing with the Versal Adaptive SoC: Network on Chip
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...

Classroom - Designing with the Versal Adaptive SoC: Quick Start
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...

Classroom - Designing with the Zynq UltraScale+ RFSoC
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...

Classroom - Designing with Verilog
This course provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and b...

Classroom - Designing with Versal AI Engine 1 - Architecture and Design Flow
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...

Classroom - Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
This course describes the system design flow and interfaces that can be used for data movement in the Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster developme...

Classroom - Designing with Versal AI Engine 3: Kernel Programming and Optimization
This course covers the advanced features of the AMD Versal™ adaptive SoC AI Engine, including kernel function development, optimizing an AI Engine kernel program, using AI Engine APIs and filter intrinsics, and debugg...