Classroom - Designing with the Zynq UltraScale+ RFSoC

This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.

The focus is on:
  • Describing the RFSoC family in general
  • Identifying applications for the RF Data Converter and SD-FEC blocks 
  • Configuring, simulating, and implementing the blocks 
  • Verifying the RF Data Converter on real hardware 
  • Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes 
  • Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device 
  • Covering Gen 1, 2, and 3 devices (DFE device details will be added in the next release) 


7/21/2025 - 7/23/2025
Time Zone : (GMT+09:00) Seoul
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Venue : KOR, Seoul - Wedu Office
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7/22/2025 - 7/24/2025
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8/12/2025 - 11/12/2026
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8/20/2025 - 8/22/2025
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8/25/2025 - 8/27/2025
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9/17/2025 - 9/19/2025
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Venue : Techsource Systems - Singapore
Address : 10 Ubi Crescent #06-48 Ubi Techpark Lobby C,Singapore,SINGAPORE