Learn how to construct, implement, and download a Dynamic Function eXchange (DFX)FPGA design using the Vivado™ Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design. ...
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity.The course covers:Learning the basics of the Ethernet standard, protocol, and OSI modelPerforming simulation to understand fund...
Provides a thorough introduction to SystemVerilog constructs for design.This focus is on:Writing RTL code using the new constructs available in SystemVerilogReviewing new data types, structs, unions, arrays, procedura...
Explore the Vivado™ IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP integrator block designs using the Vivado Design Suite.This course focuses on:Creating...
This course introduces the AMD UltraScale™ and UltraScale+™ architectures to both new and experienced designers. The emphasis is on:▪Introducing CLB resources, clock management resources (MMCM and PLL), global and reg...
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...
This course helps you to learn about Versal™ ACAP architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal ACAPDescribing the different engines available in the Ve...
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers Chip ScoPy...
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
