Classroom - Designing with SystemVerilog

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Provides a thorough introduction to SystemVerilog constructs for design.

This focus is on:

Writing RTL code using the new constructs available in SystemVerilog
Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
Targeting and optimizing Xilinx devices using SystemVerilog

7/23/2026 - 10/30/2026
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA

3/3/2027 - 9/9/2027
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT Vienna - So-Logic Office
Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA

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