Provides a thorough introduction to SystemVerilog constructs for design.
This focus is on:
Writing RTL code using the new constructs available in SystemVerilog
Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
Targeting and optimizing Xilinx devices using SystemVerilog
7/28/2025 - 10/28/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
3/26/2026 - 3/27/2026 Time Zone : (GMT-06:00) Central Time (US & Canada) Seats Remaining : 6 Venue : USA, KS, Olathe - Morgan A.P.S., Inc. Address : Olathe, KS,Morgan Advanced Programmable Systems, Inc.,Olathe,KS,USA
