This course introduces the AMD UltraScale™ and UltraScale+™ architectures to both new and experienced designers.
The emphasis is on:
▪Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
▪Describing improvements to the dedicated transceivers and Transceiver Wizard
▪Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
▪Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado™ Design Suite
8/2/2026 - 8/4/2026 Time Zone : (GMT+02:00) Israel ,Jerusalem Seats Remaining : 16 Venue : ISR, Petah-Tikva - Logtel Headquarters Address : 32 Shacham St, Ramat-Siv Industrial Park,Petah-Tikva,ISRAEL
