In this curriculum path, you will learn how to identify component, performance, I/O, and data transfer requirements at a system level. For the Versal ACAP, this includes solution application mapping to the PS, PL, and AI Engine.
Courses
Designing with the UltraScale and UltraScale+ Architectures
This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional ...
Using AMD Alveo Cards to Accelerate Dynamic Workloads
Free OnDemand Course:AMD Alveo™ accelerator cards can help you achieve the highest performance, accelerate any workload, and deploy solutions in the cloud or on premises for data center workloads.The focus of this cou...
Using Accelerated Applications with the Vision AI Starter Kit & System-on-Module (SOM)
Free OnDemand CourseThis content will help you learn about the Kria System-on-Module (SOM) and Vision AI Starter Kit, enabling you to accelerate applications using the Vision AI Starter Kit right out of the box withou...
Operating Systems and Hypervisors in Adaptive SoCs
This course provides software developers options and techniques for selecting and implementing various types of operating systems and hypervisors on AMD Zynq™ UltraScale+™ and Versal™ devices.The emphasis is on:Explor...
Zynq UltraScale+ MPSoC: Boot and Platform Management
This course provides software developers responsible for booting and platform management with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC.The emphasis is on:Reviewing the catalog o...
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...
Designing with the Versal Adaptive SoC: Serial Transceivers
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB des...
Designing with the Versal Adaptive SoC: PCI Express Systems
This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how to implement a Versal device PCI Express® solution in cu...
Learn how to effectively employ timing closure techniques. This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits Showing optimum HDL cod...
Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on: Bu...
Designing with the Versal Adaptive SoC: Memory Interfaces
This course provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture, IP generation, simulation, and implementation are covered. Additional information on PCB...
This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.The emphasis is on:Identifying the key ele...
Designing with Versal AI Engine: Kernel Programming and Optimization - 3
This course covers the advanced features of the AMD Versal™ adaptive SoC AI Engine, including kernel function development, optimizing an AI Engine kernel program, using AI Engine APIs and filter intrinsics, and debugg...
This course introduces the concepts, tools, and techniques required for software design and development for the AMD Zynq™ System on a Chip (SoC), Zynq UltraScale+™ MPSoC, and Versal™ adaptive SoC architectures using t...
Designing with the Versal Adaptive SoC: Power and Board Design
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
Learn general embedded concepts, tools, and techniques using the AMD Vivado™ Design Suite and AMD Vitis™ Unified IDE.The emphasis is on: Designing, expanding, and modifying embedded systems utilizing the features and ...
This course provides system architects with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC and Versal™ adaptive SoC devices.The emphasis is on:Utilizing power management strategies ef...
Developing Multimedia Solutions Using a Hardened VCU/VDU
Learn how to build and run complex multimedia applications targeting AMD Zynq™ UltraScale+™ MPSoC EV, Versal™ AI Core, or Versal AI Edge devices with the help of the open-source GStreamer framework.The course also ill...
Designing with the Versal Adaptive SoC: Architecture
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...
Designing with the Versal Adaptive SoC: Design Methodology
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and ther...
Designing with Versal AI Engine: Architecture and Design Flow - 1
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
This course describes the system design flow and interfaces that can be used for data movement in the AMD Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster devel...
Designing with the Versal Adaptive SoC: Quick Start
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
Designing with the Versal Adaptive SoC: Network on Chip
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
Migrating from UltraScale+ Devices to Versal Adaptive SoCs
This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+™ devices. The course also covers system design planning and partitioning...
Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, ...
This course covers the AMD Versal™ AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AMD...
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project when designing an embedded heterogeneous system...
DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) design using the Vivado™ Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.The em...
