Migrating from UltraScale+ Devices to Versal Adaptive SoCs
Course Details
Length:
16 Hours
Number of Labs:
7
Number of Chapter:
13
Current Version:
2025.1
Number of Demos:
0
Overview
This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+™ devices. The course also covers system design planning and partitioning methodologies as well as design migration considerations for different system design types.
The emphasis of this course is on:
Identifying and comparing various functional blocks in the Versal adaptive SoC to those in previous-generation UltraScale+ devices
Reviewing the approaches for migrating existing designs to the Versal adaptive SoC
Enabling top-level RTL flows for Versal devices
Identifying design migration considerations for PL-only designs and Zynq™ UltraScale+ MPSoC designs
Specifying the recommended methodology for planning a system design migration based on the system design type
Discussing AI Engine system partitioning planning
Migrating Zynq UltraScale+ MPSoC-based system-level designs to the Versal adaptive SoC
Detailing Versal device hardware debug features
What's New:
Architecture Overview for Existing Users module: Added Versal AI Edge Series Gen 2 and Prime Series Gen 2 details
System Design Migration Approach module: Updated Versal PCIe solutions and added enhanced embedded system security for Versal AI Edge Series Gen 2 and Prime Series Gen 2 details
Processing System Comparison module: Added Versal AI Edge Series Gen 2 and Prime Series Gen 2 processing system information
AI Engine Architecture Overview and Programming module: Introduced the AIE-ML v2 architecture
All labs have been updated to the latest software versions
