Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster time-to-market results.
The emphasis of this course is on:
Defining what design closure is and describing the three pillars of design closure (functional closure, timing closure, and power closure)
Using recommended coding techniques
Applying initial design checks and reviewing timing summary and methodology reports for a design
Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
Performing quality of results (QoR) assessments at different stages to improve the QoR score
Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
Applying common timing closure techniques
Optimizing SLR crossings in Versal SSIT devices
Reviewing the importance of power closure and device selection
Estimating power consumption by using the Vivado™ Design Suite Power Report utility and performing power optimization on a design
Identifying Versal™ adaptive SoC power and thermal solutions
Utilizing architecture features to improve a design's power consumption
What,s New:
All labs have been updated to the latest software versions
