Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered.
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
This course provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and b...
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
This course provides a thorough introduction to the VHDL language. The emphasis is on: Writing efficient hardware designs Performing high-level HDL simulations Employing structural, register transfer level (RTL), an...
Learn how to build and run complex multimedia applications targeting Zynq® UltraScale+™ MPSoC EV devices with the help of the GStreamer framework.This course illustrates how the use of the hardened video codec unit in...
Explore the System Generator tool and gain the expertise needed to develop advanced, low-cost DSP designs.This course focuses on:Implementing DSP functions using System Generator for DSPUtilizing design implementation...
This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR)FPGA design.You will gain a firm understanding of PR technology and learn how successfu...
