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Classroom - Zynq UltraScale+ MPSoC for the System Architect
This course provides system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.The emphasis is on:Utilizing power management strategies effectivelyLeveraging the platfo...

Design Closure Techniques
Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, ...

Designing FPGAs Using the Vivado Design Suite 1
This course offers introductory training on the AMD Vivado™ Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.The course provides experience with:Creating a Vivado Design Suite pr...

Designing FPGAs Using the Vivado Design Suite 2
Learn how to build a more effective FPGA design:The focus is on:Using synchronous design techniquesUtilizing the Vivado™ IP integrator to create a sub-systemPerforming power analysis and optimization to improve the po...

Designing FPGAs Using the Vivado Design Suite 3
Learn how to effectively employ timing closure techniques. This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits Showing optimum HDL cod...

Designing FPGAs Using the Vivado Design Suite 3 - Virtual Board
Learn how to effectively employ timing closure techniques.This course includes:Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuitsShowing optimum HDL coding techniques ...

Designing FPGAs Using the Vivado Design Suite 4
Learn how to use the advanced aspects of the Vivado™ Design Suite.The focus is on:Applying techniques to reduce delay and to improve clock skew and clock uncertaintyUtilizing floorplanning techniquesEmploying advanced...

Designing with the IP Integrator Tool
Explore the Vivado™ IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP integrator block designs using the Vivado Design Suite.This course focuses on:Creating...

Designing with the UltraScale and UltraScale+ Architectures
This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional ...

Designing with the Versal Adaptive SoC: Architecture
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...