This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.
The emphasis is on:
Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
Reviewing the various power domains and their control structure
Illustrating the processing system (PS) and programmable logic (PL)connectivity
Utilizing QEMU to emulate hardware behavior
9/29/2025 - 9/30/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : NLD - Heesch - CoreVision Headquarters Address : Cereslaan 24,Heesch,NETHERLANDS
10/30/2025 - 10/31/2025 Time Zone : (GMT+08:00) Kuala Lumpur, Singapore Seats Remaining : 8 Venue : Techsource Systems - Singapore Address : 10 Ubi Crescent #06-48 Ubi Techpark Lobby C,Singapore,SINGAPORE
