This is Session 4 in the Versal Adopter Series -Topics Include:Programming the A72, R5F and Platform Management ControllerRunning AIE graph code and RTP (run-time-parameters) on PSOverview of PS instruction set-archit...
This is Session 6 in the Versal Adopter Series -Topics Include:Utilizing and optimizing programmable logicCLB structureMemory resources, LUT-RAM, BRAM, URAMUsing and optimizing DSP58 slicesPros and cons of HDL coding ...
This is Session 5 in the Versal Adopter Series - which covers levering features and capabilities of the Versal Gen 2 devices.Topics Include:Describe the different compute resources available in the AMD Versal Gen 2 So...
This is Session 7 in the Versal Adopter Series - which covers verification of subsections and system at large.Topics Include:Best practice Versal development and debug methodologyIntro to HSDP ( High Speed Debug Port)...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provides experience with:Creating a model-based design using HDL, HLS, and AI Engine library blocks along wi...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course provides Xilinx MPSoC and ACAP developers powerful tools and techniques to hit the ground running on your Xilinx embedded design projects. Using custom labs developed by Morgan Advanced Programmable System...
This course provides embedded system developers with skills in creating an embedded Linux system targeting AMD SoCs using the Yocto Project.Setting up the Yocto environment, fetching the repositories, configuring the ...
