Provides an introduction to SystemVerilog constructs for verification.
This course covers:
Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilog
Reviewing object-oriented modeling, data types, reusable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI)
7/31/2025 - 10/29/2026 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 10 Venue : AUT Vienna - So-Logic Office Address : Rosengasse 29,Gerasdorf / Kapellerfeld,AUSTRIA
7/16/2026 - 7/17/2026 Time Zone : (GMT-06:00) Central Time (US & Canada) Seats Remaining : 6 Venue : USA, IL, Schaumburg - Morgan A.P.S., Inc. Address : Schaumburg,IL,USA
11/8/2026 - 11/11/2026 Time Zone : (GMT+02:00) Israel ,Jerusalem Seats Remaining : 16 Venue : ISR, Petah-Tikva - Logtel Headquarters Address : 32 Shacham St, Ramat-Siv Industrial Park,Petah-Tikva,ISRAEL
