Learn when and how to apply signal integrity techniques to high-speed interfaces between AMD FPGAs and other components.
This course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics Hyper Lynx. Other topics include managing PCB effects and on-chip termination.
5/24/2026 - 5/27/2026 Time Zone : (GMT+02:00) Israel ,Jerusalem Seats Remaining : 16 Venue : ISR, Petah-Tikva - Logtel Headquarters Address : 32 Shacham St, Ramat-Siv Industrial Park,Petah-Tikva,ISRAEL
