To overcome bottlenecks due to sequential processing in embedded systems FPGAs provide massive parallelism and application fitted data path. Xilinx supports such heterogenous FPGA and CPU designs with the Vitis Unified Software Platform. It allows projects for low level hardware drivers to be setup in one toolchain with the datapath projects that use high-level programming languages, e.g. OpenCL API for offloading functionality from CPU to FPGA kernels. This program gets the software developer started on the Vitis Unified Software Platform by introducing the Zynq SoC and MPSoC architectures. Software development knowledge for the standalone platform is provided to cover the basic operation and low level services. Application development on the OS level is combined with insight into driver development. On this platform all is set for development, debug, and profiling of C/C++ and RTL applications targeting data center (DC) and embedded (Edge) e.g. on the XILINX ALVEO accelerator board. Optimization topics and best practices will be provided all along.
8/25/2025 - 8/29/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Freiburg - PLC2 Office Address : Hugstmattweg 30,Freiburg,GERMANY
11/10/2025 - 11/14/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 12 Venue : DEU, Berlin - TBD PLC2 Venue Address : TBD,Berlin,GERMANY
