This is Session 7 in the Versal Adopter Series - which covers verification of subsections and system at large.Topics Include:Best practice Versal development and debug methodologyIntro to HSDP ( High Speed Debug Port)...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provides experience with:Creating a model-based design using HDL, HLS, and AI Engine library blocks along wi...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course provides Xilinx MPSoC and ACAP developers powerful tools and techniques to hit the ground running on your Xilinx embedded design projects. Using custom labs developed by Morgan Advanced Programmable System...
This course provides embedded system developers with skills in creating an embedded Linux system targeting AMD SoCs using the Yocto Project.Setting up the Yocto environment, fetching the repositories, configuring the ...
Provides experiences system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.This course covers:Identifying the features and benefits of the Zynq SoC architectureDes...
This course provides system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.The emphasis is on:Utilizing power management strategies effectivelyLeveraging the platfo...
Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, ...
