Classroom - VIV-ADV: Designing FPGAs Using the Vivado Design Suite Advanced (FUAM)

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado logic analyzer. These modules also tackle the most sophisticated aspects of the Vivado Design Suite and Xilinx hardware. The knowledge enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.