This is Session 7 in the Versal Adopter Series - which covers verification of subsections and system at large.
Topics Include:
Best practice Versal development and debug methodology
Intro to HSDP ( High Speed Debug Port)
Establishing simulation break-points for PS application and AIE code
Leveraging Vivado logic analyzer for PL
Cross-triggering techniques for PL and PS
Configuration and debugging
System debugging
Using trace events for AIE debugging
ChipScoPy overview
Hard block debugging
Using Vitis Analyzer
12/9/2025 - 12/9/2025 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 6 Venue : USA, CA, Irvine - Avnet Office Address : 220 Commerce #100,Irvine,CA,USA
12/10/2025 - 12/10/2025 Time Zone : (GMT-08:00) Pacific Time (US & Canada) Seats Remaining : 6 Venue : Avnet San Diego Address : 13500 Evening Creek Dr. N,Suite 400,San Diego,CA,USA
