This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how to implement a Versal device PCI Express® solution in cu...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB des...
In this seminar we would explore the AMD Versal™ adaptive SoC heterogeneous architecture and concentrate in three important aspects of the architecture (i) the programmable network on chip (NoC), (ii) the memory inter...
We will derive a complete data driven design from start in AMD VivadoTM, where the general architecture is visible already to guide into the common features. The sessions touch further on the traditional embedded desi...
This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+™ devices. The course also covers system design planning and partitioning...
This course provides software developers options and techniques for selecting and implementing various types of operating systems and hypervisors on AMD Zynq™ UltraScale+™ and Versal™ devices.The emphasis is on:Explor...
With the newXILINX ACAP family (Adaptive Compute Acceleration Platform) hardware developersare enabled for the classic methods of HDL development, i.e. also by using HLStool. And with Vitis a huge capability of method...
