This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how to implement a Versal device PCI Express® solution in cu...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB des...
If you need to produce complex designs with a broad variety of specific tasks oryou are coming across the AMD adaptive SoC portfolio from a technology step upfrom FPGAs, all features provided by device families like A...
This two-part free workshop explores the tools and techniques available to debug AMD Versal devices. We'll investigate debugging the fabric and hard blocks, as well as APIs which provide a Python interface for program...
Gain a comprehensive understanding of the AMD Versal adaptive SoC architecture building blocks, such as programmable logic (PL), high-speed I/O, clocking, processing system (CIPS), Intelligent Engines (AIE), and the p...
This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+™ devices. The course also covers system design planning and partitioning...
This course provides software developers options and techniques for selecting and implementing various types of operating systems and hypervisors on AMD Zynq™ UltraScale+™ and Versal™ devices.The emphasis is on:Explor...
With the newXILINX ACAP family (Adaptive Compute Acceleration Platform) hardware developersare enabled for the classic methods of HDL development, i.e. also by using HLStool. And with Vitis a huge capability of method...
