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CURRICULUM BY DESIGN PROCESS

System Integration and Validation

In this curriculum path, you will learn how to integrate and validate system functional performance, including timing, resource use, and power.
Courses
Using Accelerated Applications with the Vision AI Starter Kit & System-on-Module (SOM)
Free OnDemand CourseThis content will help you learn about the Kria System-on-Module (SOM) and Vision AI Starter Kit, enabling you to accelerate applications using the Vision AI Starter Kit right out of the box withou...
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Zynq UltraScale+ MPSoC: Boot and Platform Management
This course provides software developers responsible for booting and platform management with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC.The emphasis is on:Reviewing the catalog o...
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Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...
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Designing with the Versal Adaptive SoC: Hardware Debug
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers ChipScoPy ...
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Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on: Bu...
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Migrating to the Vitis Unified IDE
This course demonstrates the tools and techniques required for embedded software design and development using the AMD Vitis™ Unified IDE.The emphasis of this course is on:Reviewing the basics of the embedded software ...
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Designing with the IP Integrator Tool
Explore the Vivado™ IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP integrator block designs using the Vivado Design Suite.This course focuses on:Creating...
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Vitis Model Composer: A MATLAB and Simulink-based Product
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provides experience with:Creating a model-based design using HDL, HLS, and AI Engine library blocks along wi...
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Zynq UltraScale+ MPSoC for the Hardware Designer
This course provides hardware designers with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC family from a hardware architectural perspective.The emphasis is on:Identifying the key ele...
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Embedded Systems Software Design
This course introduces the concepts, tools, and techniques required for software design and development for the AMD Zynq™ System on a Chip (SoC), Zynq UltraScale+™ MPSoC, and Versal™ adaptive SoC architectures using t...
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High-Level Synthesis with the Vitis Unified IDE (HLS)
This course provides a thorough introduction to high-level synthesis (HLS) using the AMD Vitis™ Unified IDE.The focus of this course is on:Converting C/C++ designs into RTL implementationsLearning the HLS component de...
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Embedded Systems Design
Learn general embedded concepts, tools, and techniques using the AMD Vivado™ Design Suite and AMD Vitis™ Unified IDE.The emphasis is on: Designing, expanding, and modifying embedded systems utilizing the features and ...
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Adaptive SoCs for System Architects
This course provides system architects with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC and Versal™ adaptive SoC devices.The emphasis is on:Utilizing power management strategies ef...
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Designing with the Versal Adaptive SoC: Architecture
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...
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Designing with Versal AI Engine: Quick Start
This course covers the AMD Versal™ AI Engine architecture and memory modules, programming the AI Engine (kernels and graphs), using the DSP Library, developing AI Engine designs using AMD Vitis™ Model Composer, and de...
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Designing with the Versal Adaptive SoC: Design Methodology
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and ther...
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Designing with Versal AI Engine: Architecture and Design Flow - 1
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
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Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
This course describes the system design flow and interfaces that can be used for data movement in the AMD Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster devel...
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Designing with the Versal Adaptive SoC: Quick Start
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
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Designing with the Versal Adaptive SoC: Network on Chip
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
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Migrating from UltraScale+ Devices to Versal Adaptive SoCs
This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+™ devices. The course also covers system design planning and partitioning...
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Designing with the Zynq UltraScale+ RFSoC
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
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Embedded Heterogeneous Design
This course covers the AMD Versal™ architecture and illustrates the tool flow for developing HLS and AI Engine components as well as integrating an entire system project when designing an embedded heterogeneous system...
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DFX - Designing with Dynamic Function eXchange Using the Vivado Design Suite
Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) design using the Vivado™ Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.The em...
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