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Designing with the Versal Adaptive SoC: Architecture
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as the programmable logic, high-speed I/O, clocking, processing system, AI Engines, and the programmable network on chip (NoC). Also learn ho...

Designing with the Versal Adaptive SoC: Hardware Debug
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers ChipScoPy ...

Designing with the Versal Adaptive SoC: Memory Interfaces
This course provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture, IP generation, simulation, and implementation are covered. Additional information on PCB...

Designing with the Versal Adaptive SoC: Network on Chip
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...

Designing with the Versal Adaptive SoC: Quick Start
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...

Designing with the Versal Adaptive SoC: Serial Transceivers
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB des...

Designing with the Zynq UltraScale+ RFSoC
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...

Designing with Verilog
This course provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and b...

Designing with Versal AI Engine: Graph Programming with AI Engine Kernels - 2
This course describes the system design flow and interfaces that can be used for data movement in the AMD Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster devel...

Designing with Versal AI Engine: Kernel Programming and Optimization - 3
This course covers the advanced features of the AMD Versal™ adaptive SoC AI Engine, including kernel function development, optimizing an AI Engine kernel program, using AI Engine APIs and filter intrinsics, and debugg...