Designing with the Versal Adaptive SoC: Network on Chip
Course Details
Length:
13 Hours
Number of Labs:
5
Number of Chapter:
10
Current Version:
2025.2
Number of Demos:
0
Overview
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC can be configured to access DDR memory controllers and HBM memory controllers.
The emphasis of this course is on:
Enumerating the major components comprising the NoC architecture in the Versal adaptive SoC
Implementing a basic Versal NoC design using the Vivado™ IP integrator
Accessing the Versal NoC using the modular NoC flow
Configuring the DDR memory controller for accessing DDR memory
Configuring and tunning the NoC for efficient data movement
What's New:
Added a new module on NoC DDR5 Memory Controller
All labs have been updated to the latest software versions
