This course helps you to learn about Versal Adaptive SoC architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal Adaptive SoCDescribing the different engines avai...
This course helps you to learn about Versal™ Adaptive SoC architecture and design methodology. The emphasis of this course is on:▪ Reviewing the architecture of the Versal Adaptive SoC▪ Describing the different engine...
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and ther...
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
Thiscourse introduces the features and capabilities of the PCIe® and Cache CoherentInterconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how toimplement a Versal device PCI Express® solution in custo...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered. The emphasis of ...
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on: Describing the...
This course provides a thorough introduction to the Verilog language. The emphasis is on: Writing efficient hardware designs Performing high-level HDL simulations Employing structural, register transfer level (RTL), ...
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
