This course provides a thorough introduction to the Verilog language. The emphasis is on: Writing efficient hardware designs Performing high-level HDL simulations Employing structural, register transfer level (RTL), a...
This course is a combination of two courses (AIE1 & AIE2) related to the Versal™ AI Engine which are often taken back to back. This combination offers students the savings of time and money by removing the redundancie...
This course provides a thorough introduction to the VHDL language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and beha...
Learn how to employ serial transceivers in 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC designs.The focus is on:Identifying and using the features of the serial transceiver blocks, such as 8B/10...
Implement neural networks on cloud and edge platforms using the Vitis™ AI development platform. The emphasis of this course is on: Illustrating the Vitis AI tool flow, including optimization and compilation Exploring ...
Learn how to build and run complex multimedia applications targeting Zynq® UltraScale+™ MPSoC EV devices with the help of the GStreamer framework.This course illustrates how the use of the hardened video codec unit in...
This course isdesigned for engineers developing software for platforms based around any ofthe Arm® Cortex®-M Series processors. The course includes an introduction tothe ARM product range and supporting IP, the proces...
AMD Vitis™ Model Composer is the updated version of DSP System Generator and now provides support for HDL, HLS (High Level Synthesis) and AIE (AI Engine) development. Discover how this powerful combination of tools gi...
This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR)FPGA design.You will gain a firm understanding of PR technology and learn how successfu...
