Virtual - Designing with the Zynq UltraScale+ RFSoC

This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.

The focus is on:
  • Describing the RFSoC family in general 
  • Identifying applications for the RF Data Converter and SD-FEC blocks 
  • Configuring, simulating, and implementing the blocks 
  • Verifying the RF Data Converter on real hardware 
  • Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes 
  • Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device 
  • Covering Gen 1, 2, and 3 devices (DFE device details will be added in the next release) 

11/19/2025 - 11/21/2025
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11/19/2025 - 11/21/2025
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12/1/2025 - 12/3/2025
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12/2/2025 - 12/4/2025
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2/9/2026 - 2/12/2026
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2/24/2026 - 2/27/2026
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5/5/2026 - 5/7/2026
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