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Virtual - Designing with the Zynq UltraScale+ RFSoC

This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.

The focus is on:
  • Describing the RFSoC family in general 
  • Identifying applications for the RF Data Converter and SD-FEC blocks 
  • Configuring, simulating, and implementing the blocks 
  • Verifying the RF Data Converter on real hardware 
  • Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes 
  • Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device 
  • Covering Gen 1, 2, and 3 devices (DFE device details will be added in the next release) 

7/20/2026 - 7/22/2026
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 6
Venue : Online - Morgan A.P.S., Inc.
Address :
8/19/2026 - 8/21/2026
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 6
Venue : Online - Morgan A.P.S., Inc.
Address :
8/26/2026 - 8/28/2026
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 6
Venue : Online - Morgan A.P.S., Inc.
Address :
12/1/2026 - 12/3/2026
Time Zone : (GMT-05:00) Eastern Time (US & Canada)
Seats Remaining : 20
Venue : Online - BLT
Address : www.bltinc.com
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