This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.
The focus is on:
Describing the RFSoC family in general
Identifying applications for the RF Data Converter and SD-FEC blocks
Configuring, simulating, and implementing the blocks
Verifying the RF Data Converter on real hardware
Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes
Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device
Covering Gen 1, 2, and 3 devices (DFE device details will be added in the next release)
12/1/2026 - 12/3/2026 Time Zone : (GMT-05:00) Eastern Time (US & Canada) Seats Remaining : 20 Venue : Online - BLT Address : www.bltinc.com
