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Virtual - Designing with the Zynq UltraScale+ RFSoC

This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.

The focus is on:
  • Describing the RFSoC family in general 
  • Identifying applications for the RF Data Converter and SD-FEC blocks 
  • Configuring, simulating, and implementing the blocks 
  • Verifying the RF Data Converter on real hardware 
  • Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes 
  • Identifying proper layout and PCB considerations since the Zynq UltraScale+ RFSoC is both a high-speed and an analog and digital device 
  • Covering Gen 1, 2, and 3 devices (DFE device details will be added in the next release) 

1/21/2026 - 1/23/2026
Time Zone : (GMT-06:00) Central Time (US & Canada)
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Venue : Online - Morgan A.P.S., Inc.
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2/3/2026 - 2/5/2026
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Venue : Online - Morgan A.P.S., Inc.
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2/9/2026 - 2/12/2026
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Venue : Online - Doulos Inc
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2/24/2026 - 2/27/2026
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Venue : Online - Doulos Ltd
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3/23/2026 - 3/25/2026
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Venue : Online - Morgan A.P.S., Inc.
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4/22/2026 - 4/24/2026
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4/28/2026 - 4/30/2026
Time Zone : (GMT-05:00) Eastern Time (US & Canada)
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Venue : Online - BLT
Address : www.bltinc.com
4/29/2026 - 5/1/2026
Time Zone : (GMT-06:00) Central Time (US & Canada)
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Venue : Online - Morgan A.P.S., Inc.
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