This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the ...
The design flow of AMD Adaptive SoCs aggregates diverse content for the different targets within these devices. Surely embedded software is one of the prominent project types that needs to be conquered but also many o...
This online workshop introduces key concepts, tools, and techniques required for design and development using AMD embedded x86 processors, including Zen 5, Epyc, and Ryzen.This course provides a structured approach to...
This online workshop introduces key concepts, tools, and techniques required for design and development Versal AI Engine using Vitis Model Composer for model-based designs. This course provides experience with using t...
The Versal™ AI Engines are a central innovation within the Versal Adaptive SoC family, designed to provide high-performance, energy-efficient compute capabilities for AI, signal processing, and data-intensive applicat...
During the event, you'll be introduced to the new AMD Versal™ platform. Explore the heterogeneous Versal™ adaptive SoC architecture containing programmable network-on-chip (NoC) and AI engines, and learn how to use di...
Versal Adaptive SoCs Quick Start Workshop: A Guide to Integration and ImplementationThis course focuses on the Versal adaptive SoC architecture.BLT Engineers have successfully deployed designs to Versal devices for Cl...
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on:Usi...
With the VersalAdaptive Compute Acceleration Platform (ACAP) family XILINX introduces versionsof these devices with a special feature, the AI Engine. The AI Engine offershigh performance, low latency capabilities for ...
Increase VHDL proficiency by learning advanced techniques for writing more robust and reusable code.The focus is on:Writing efficient and reusable RTL, testbenches, and packagesCreating self-testing testbenchesCreatin...
