This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the ...
Do you find it challenging to close timing in your FPGA design?This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achi...
This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AM...
This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the ...
This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs.The emphasis of this course is on:Introduct...
Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most ou...
During the event, you'll be introduced to the new AMD Versal™ platform. Explore the heterogeneous Versal™ adaptive SoC architecture containing programmable network-on-chip (NoC) and AI engines, and learn how to use di...
In this seminar we would explore the AMD Versal™ adaptive SoC heterogeneous architecture and concentrate in three important aspects of the architecture (i) the programmable network on chip (NoC), (ii) the memory inter...
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on:Usi...
