With the VersalAdaptive Compute Acceleration Platform (ACAP) family XILINX introduces versionsof these devices with a special feature, the AI Engine. The AI Engine offershigh performance, low latency capabilities for advanced data processing. Thiscourse enables algorithm programmers to deploy C/ C++ kernels on Versal AI Engine.First, the basic elements of the Versal AI Engine are described with regards tothe internal VLIW processing units, interfaces and connections to data path andmemory hierarchy in the regular grid of the AIE tiles are presented. With theVitis tools the AI Engine is set up to run acceleration functions written inC/C++ code. This shows how to implement a discrete AI Engine kernel includingdebugging capabilities and analysis features of the Vitis Toolchain alongexamples and labs. For signal processing setups a tool flow is presented thatuses dataflow graphs to connect multiple kernels and shows the capabilities ofthe Versal AI Engine array. Deploying these dataflow graphs the course moves onto the system level design flow with AI Engine based kernels in Vitis. Animportant aspect of system design with Versal devices is applicationpartitioning between the different heterogeneous compute engines that areavailable. To create heterogeneous system design, the data flow graph may routemultiple compute domains as PL and AI Engine. The common features to interfacethese graph elements effectively, such as streams, are explained and can beexperienced in hands on lab exercises.
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