Free Workshop: Virtual - Designing with Versal AI Engine: Architecture and Design Flow (Electratraining)

The Versal™ AI Engines are a central innovation within the Versal Adaptive SoC family, designed to provide high-performance, energy-efficient compute capabilities for AI, signal processing, and data-intensive applications. This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), and how to analyze a kernel program by using various debugger features. Developing AI Engine DSP designs using AMD Vitis™ Model Composer is also demonstrated. In addition, advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade streams, buffer location constraints, runtime parameterization, and APIs to update and read runtime parameters, recovered. By default, the course will be taught in Spanish.

1/29/2026 - 1/29/2026
Time Zone : (GMT+01:00) Brussels, Copenhagen, Madrid, Paris
Seats Remaining : 16
Venue : ESP, Madrid - Universidad Autonoma de Madrid
Address : Fco Tomas y Valiente 11,School of Engineering,Madrid,SPAIN