With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs. The course provides experience with: Creating a model-based design using HDL, HLS, and AI Engine library blocks.
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...
This course provides embedded system developers with skills in creating an embedded Linux system targeting AMD SoCs using the Yocto Project.Setting up the Yocto environment, fetching the repositories, configuring the ...
Provides experiences system architects with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.This course covers:Identifying the features and benefits of the Zynq SoC architectureDes...
This course provides system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family.The emphasis is on:Utilizing power management strategies effectivelyLeveraging the platfo...
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