At the beginning of this class, an introduction to the vocabulary and the transmission protocol are given, along with details on the structure and content of data packets. This is a solid foundation for building yo...
This course introduces the features and capabilities of the serial transceiver blocks in the UltraScale™ architectures. Learn how to implement UltraScale™/UltraScale+™transceiver solutions in custom applications to im...
With the newXILINX ACAP family (Adaptive Compute Acceleration Platform) hardware developersare enabled for the classic methods of HDL development, i.e. also by using HLStool. And with Vitis a huge capability of method...
This 3-day coursewill enable the software developer to get the best possible start on softwaredevelopment for the Versal ACAP family. This first explains the Versal ACAParchitecture and the unified Vitis Software Deve...
The Versal™ architecture allows very fast interfaces to external components based on significantly improved silicon structures as well as new IP Core configuration wizards. Realization challenges are shifting from ...
This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal™ device PCIe® solution in custom applications to im...
VHDL is a strongly typed hardware description language that prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the Register Transfer Level (RTL) to design digital circuits of any comp...
Programmable logic devices like FPGAs have been established in daily life. They can be found in mobile phones, IoT devices, cars, or cloud data centers. Their area of operation is as broad as their size. FPGAs are use...
This coursepresents the Vitis AI development Toolkit for the AI inference on XilinxHardware platforms in conjunction with DNN algorithms, model training,associated frameworks for development and deploying it on Alveo™...
