The main pillars are a unified and scalable database allowing great cross-probing possibilities and a unique test environment for a shortened learning curve. In addition, increased adherence to industry standards such as AMBA™ AXI4, IP-XACT (for metadata for self-developed IP cells), Tool command Language (Tcl), Synopsys Design Constraints (SDC), etc. allows easy scalability and simplified automation of the development process. Vivado™ is conceptually designed in a way to deal with all aspects (logic, SW, I/O, mixed signal, etc.) of programmable technology and this is for designs of a complexity of up to 100M ASIC gates.
This class gives a detailed discussion of the creation of XDC (AMD Design Constraints) and the static timing analysis. On top, proper usage of FPGA resources is discussed along with how the unified Vivado™ design database can be used efficiently for e.g., analysis purposes.
9/17/2025 - 9/19/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
11/19/2025 - 11/21/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
