This course introduces the features and capabilities of the serial transceiver blocks in the UltraScale™ architectures. Learn how to implement UltraScale™/UltraScale+™transceiver solutions in custom applications to improve time to market. This workshop enables designers to effectively use all available features of the serial transceivers, define the interfaces and attributes necessary for using the features, and instantiate the serial transceiver primitives available with the transceiver wizards which are an integral part of the IP catalog. This allows to implement project-specific or standardized serial interfaces. The IBERT design is used to show an effective verification of the serial transmission link. Signal-integrity topics, including a simulation example and pointers on board design, provide practical tips for implementation. During the training, the target technology will be the Kintex™ UltraScale™ FPGAKCU105 evaluation board.
9/15/2025 - 9/17/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
