Virtual - Compact FPGA Circuit Design Technique (PLC2 version)

The general introduction to "Compact FPGA Circuit Design Technique" discusses the basic circuit elements of an FPGA. This comprises combinational and sequential circuits such as multiplexers, lookup tables, flip-flops, RAMs, adders, multipliers, clock generators, and I/Os. Subsequently, more complex circuits like comparators, counters, shift registers, FIFOs and Finite State Machines (FSM) are composed of base elements. The knowledge gained in this way can now be transferred to the Xilinx® UltraScale+™ technology. In order to create a wider theoretical and practical groundwork, additional topics are clock networks, reset distribution as well as asynchronous vs. synchronous circuits. This also includes designs with multiple clock networks, data exchange, and synchronization between clock domains (Clock Domain Crossing – CDC).

8/6/2025 - 8/8/2025
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 6
Venue : Online - PLC2
Address :
10/15/2025 - 10/17/2025
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 6
Venue : Online - PLC2
Address :