This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how to implement a Versal device PCI Express® solution in cu...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB des...
Learn about the AMD Versal™ AI Edge Series Gen 2 and Prime Series Gen 2 adaptive SoC architectures, which combine programmable logic with a new high-performance processing system and next-generation AI Engines. Also l...
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
This course provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and b...
This course outlines the architecture of AMD Versal™ AI Engine ML v2 (AIE-ML v2), a part of AMD Versal AI Edge Series Gen 2 devices, and explores the features and key architectural enhancements with this iteration of ...
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
