Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on: Bu...
This course provides system architects with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC and Versal™ adaptive SoC devices.The emphasis is on:Utilizing power management strategies ef...
Learn how to effectively employ timing closure techniques. This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits Showing optimum HDL cod...
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and ther...
This course describes the tools and techniques available to debug AMD Versal™ devices. You will learn about features for debugging the fabric (programmable logic) and the hard blocks. The course also covers ChipScoPy ...
This course provides a system-level understanding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture, IP generation, simulation, and implementation are covered. Additional information on PCB...
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered.The emphasis of t...
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge ...
This course describes the AMD Versal™ AI Engine architecture, the data communications within an AI Engine array and between the PL and AI Engines, how to program the AI Engines (single kernel programming and multiple ...
