Designing with the Spartan UltraScale+ FPGA: Architecture
Course Details
Length:
15 Hours
Number of Labs:
4
Number of Chapter:
22
Current Version:
2025.1
Number of Demos:
0
Overview
Learn about the key features and architecture of the AMD Spartan™ UltraScale+™ FPGA, including its advanced I/O, high-speed transceivers, substantial built-in and external memory, PCIe® Gen4 connectivity, and modern security. Recognize how these features provide a versatile, cost-optimized, and power-efficient platform for diverse applications.
The emphasis of this course is on:
Describing the key features and fundamental blocks of the Spartan UltraScale+ FPGA architecture
Describing Spartan UltraScale+ clocking, including buffer types, clock management tiles, and routing for enhanced timing
Describing the various on-chip memory resources available in the Spartan UltraScale+ architecture
Utilizing the advanced I/O capabilities for various connectivity needs
Identifying the high-speed transceivers for use in applications such as PCIe Gen4
Explaining the configuration process for Spartan UltraScale+ devices
Outlining the platform security framework and advanced security features
Leveraging the Power Design Manager (PDM) tool for power estimation
