Designing with the Versal Adaptive SoC: Design Methodology
Course Details
Length:
27 Hours
Number of Labs:
9
Number of Chapter:
23
Current Version:
2025.1
Number of Demos:
0
Overview
Use different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning, design closure, power, and thermal solutions to enhance the performance of a design.
The emphasis of this course is on:
Demonstrating the embedded software development flow for Versal devices
Demonstrating the AI Engine development flow
Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
Leveraging the Power Design Manager (PDM) tool for power estimation
Identifying Versal adaptive SoC power and thermal solutions
Enabling top-level RTL flows for Versal devices
Applying common timing closure techniques
Performing device configuration and debugging
Improving Versal adaptive SoC system performance
Performing system-level simulation
What's New:
Added new modules: Using the AMD Embedded Development Framework (EDF) & Introduction to the Software Hardware Exchange Loop (SHEL) Flow
Added bare-metal and Linux software stack details for Versal AI Edge Series Gen 2 and Prime Series Gen 2 in Software Stack module
Added enhanced embedded system security for Versal AI Edge Series Gen 2 and Prime Series Gen 2 in Security Management and Safety Features module
Introduced segmented configuration for Versal AI Edge Series Gen 2 and Prime Series Gen 2 in Segmented Configuration module
Added new lab on Using the Modular NoC Flow in an RTL Design
All labs have been updated to the latest software versions
