Learn how to apply UltraFast Design Methodology timing closure techniques and to achieve timing closure for a given design. The emphasis of this course is on:Applying initial design checks and reviewing timing summary...
Learn how to improve design speed and reliability by using the UltraFast™ Design Methodology and the Vivado™ Design Suite. The focus is on:Optimizing system reset design and synchronization circuits Employing best pra...
The UVM Adopter Class will prepare you for full verification project readiness by focusing on the in-depth, practical application of the Universal Verification Methodology using commercial verification tools.
With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...
This course provides an overview of the hard block capabilities for the Versal ACAPThe focus is on:Describe the Versal™ ACAP architecture at a high levelDescribe the various engines in the Versal ACP device Use the va...
VHDL for Designers (Xilinx) prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essentia...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provides experience with: Creating a model-based design using HDL, HLS, and AI Engine library blocks along w...
This course for experienced Xilinx FPGA designers allows you to maximize QoR in terms of clock rates, timing closure and power management. This class also enhance both individual and team productivity. The complete ra...
This course covers all essential Xilinx FPGA design concepts. It affords you a solid foundation for leveraging Xilinx tools and technology. We cover every aspect of FPGA design, from architectural considerations, to d...
