Learn how to apply UltraFast Design Methodology timing closure techniques and to achieve timing closure for a given design. The emphasis of this course is on:
- Applying initial design checks and reviewing timing summary and methodology reports for a design
- Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
- Identifying and resolving setup and hold violations
- Reducing logic delays, net delays, and congestion in a design
- Improving clock skew and clock uncertainty
- Performing Pblock-based and super logic region (SLR)-based analysis to identify challenges and improve timing closure
- Performing quality of results (QoR) assessments at different stages to improve the QoR score
- Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
