Explore the Vivado™ IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP integrator block designs using the Vivado Design Suite. This course focuses on: Creati...
This course introduces the AMD UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regio...
This four-day LIVE Online Training (LOT) course is structured to provide FPGA HW, SW and system architects with an overview of the capabilities and support for the Zynq UltraScale+ MPSoC family.
This course helps you to learn about Versal Adaptive SoC architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal Adaptive SoCDescribing the different engines avai...
This course helps you to learn about Versal™ Adaptive SoC architecture and design methodology. The emphasis of this course is on:Reviewing the architecture of the Versal Adaptive SoCDescribing the different engines av...
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the N...
Thiscourse introduces the features and capabilities of the PCIe® and Cache CoherentInterconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how toimplement a Versal device PCI Express® solution in custo...
This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal™ adaptive SoC. PCB design considerations for the Versal devices are also covered. The emphasis of ...
This course provides an overview of the hard block capabilities for the AMD Zynq™ UltraScale+™ RFSoC family with a special emphasis on the RF Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the ...
This course provides a thorough introduction to the Verilog language. The emphasis is on: Writing efficient hardware designs Performing high-level HDL simulations Employing structural, register transfer level (RTL), a...
