Designing with the Versal Adaptive SoC: Network on Chip
Course Details
Length:
13 Hours
Number of Labs:
5
Number of Chapter:
9
Current Version:
2025.1
Number of Demos:
0
Overview
This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC can be configured to access DDR memory controllers and HBM memory controllers.
The emphasis of this course is on:
Enumerating the major components comprising the NoC architecture in the Versal adaptive SoC
Implementing a basic Versal NoC design using the Vivado™ IP integrator
Accessing the Versal NoC using the modular NoC flow
Configuring the DDR memory controller for accessing DDR memory
Configuring and tunning the NoC for efficient data movement
What's New:
Architecture Overview for Existing Users module: Added Versal AI Edge Series Gen 2 and Prime Series Gen 2 details
NoC DDR Memory Controller module: Added NoC DDR5 memory controller support and configuration details
Added a new lab on Introduction to the AXI NoC2 and DDRMC5
NoC Performance Tuning module: Added information on configuring multi-phase NoC modes
All labs have been updated to the latest software versions
