With the VersalAdaptive Compute Acceleration Platform (ACAP) family XILINX introduces versionsof these devices with a special feature, the AI Engine. The AI Engine offershigh performance, low latency capabilities for ...
Increase VHDL proficiency by learning advanced techniques for writing more robust and reusable code.The focus is on:Writing efficient and reusable RTL, testbenches, and packagesCreating self-testing testbenchesCreatin...
The AMD Vivado™ design suite tool provides many features which offer valuable features for the experienced hardware designer. Extended tool features are needed for a higher productivity in the development process: the...
This course explains the features of the CPUs in the processing system to effectively design embedded software for operating systems and complex applications. In systems deploying multiple independent processors in op...
This course covers the software aspects ofdesigning with an Arm® Cortex®-A53 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® UltraScale+™ implementation choices.Topics include the...
SystemVerilog (IEEE 1800™), the successor to the Verilog® hardware description language, has become the dominant language standard for functional verification. SystemVerilog significantly enhances the capabilities of ...
This course provides experience with using the Vitis™ Model Composer tool for model-based designs focusing on UltraScale+™ and Versal™ technologies. With MATLAB™ and Simulink™,Vitis™ Model Composer offers the DSP deve...
This workshop provides an overview of implementation strategies and tooling for processing the massive computation of deep neural networks on programmable devices. The AMD adaptive SoCs are a suitable target for these...
