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Virtual - Scripting the AMD Hardware Design Flow (PLC2 version)
Scripting the hardware design flow is a very essential need and there are many advantages seen for the hardware design flow: Reproducibility of p&r runs, reusability for the IP repositories, AMD tool release managemen...

Virtual - Signal Integrity and Board Design for Xilinx FPGAs
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components.This course combines design techniques and methodology with relevant background concepts of hi...

Virtual - SpeedingEdge - Signal Integrity and High-Speed Design (Doulos version)
This highly practical course is designed to take the student through the entire process involved in designing and fabricating high-speed PCBs. It begins with the fundamentals of electromagnetic fields and the behavior...

Virtual - SystemC Modeling Using TLM-2.0 (Doulos Version)
SystemC Modeling using TLM-2.0 is the authoritative industry standard 3-day training class teaching the final OSCI TLM-2.0 transaction-level modeling standard, which was itself released in June 2008. This class was de...

Virtual - SystemVerilog for Design and Verification (Doulos Version)
SystemVerilog (IEEE 1800™), the successor to the Verilog® hardware description language, has become the dominant language standard for functional verification. SystemVerilog significantly enhances the capabilities of ...

Virtual - SystemVerilog for New Designers (Doulos version)
System Verilog for New Designers ONLINE prepares the engineer for practical project readiness for FPGA or ASIC design, including RTL synthesis, block-level test benches, and FPGA design flows. Delegates targeting FPGA...

Virtual - UVM Adopter Class (Doulos course)
The UVM Adopter Class will prepare you for full verification project readiness by focusing on the in-depth, practical application of the Universal Verification Methodology using commercial verification tools.

Virtual - Versal Adaptive SoC for the System Architect (PLC2 version)
With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family -Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity...

Virtual - VHDL for Designers (Doulos version)
VHDL for Designers (Xilinx) prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices, this module also provides the essentia...

Virtual - Vitis Model Composer: A MATLAB and Simulink-based Product
This course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provides experience with: Creating a model-based design using HDL, HLS, and AI Engine library blocks along w...