With the VersalAdaptive Compute Acceleration Platform (ACAP) family XILINX introduces versionsof these FPGA with a special feature, the AI Engine. The AI Engine offers highperformance, low latency capabilities for advanced data processing. This course shows the application acceleration with C/C++ kernels on Versal AIEngine. From start the elements of the Versal AI Engine are described, the VLIWprocessing unit, the connectivity through the available interfaces and thememory hierarchy in the regular grid of these AIE tiles. With the Vitis toolsthe AI Engine is set up to run acceleration functions written in C/C++ code. Wewill show how to implement discrete AI kernels with the full set of intrinsicfunctions with XChessDE or the Vitis tool-chain. Upon understanding basickernel programming a tool flow is presented that uses dataflow graphs toconnect multiple kernels. Deploying these dataflow graphs this course alsoshows the system level design flow with AI Engine based kernels in Vitis. Thedata movement between compute domains, i.e. within the AI Engine and towardsNoC and PL is presented and the different interface types and connectioncapabilities are explained. This course teaches how to analyze and optimizedesigns with the tooling in the Vitis platform. To deploy such heterogeneous systems,the data flow graph may route multiple compute domains as PL and AI Engine. Theadvanced features to interface these graph elements effectively, such asstreams, cascade stream, buffer location constraints, run-time parameterizationand respective APIs are explained and can be experienced in hands on labexercises. It will be shown how such data processing graphs can be added into aVersal device system design.
10/6/2025 - 10/10/2025 Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna Seats Remaining : 6 Venue : Online - PLC2 Address :
